1. Field of the Invention
The present invention relates to circuitry which generates a clock for controlling signal processing devices integrated on a semiconductor chip. More particularly, the invention relates to a spread spectrum clock generator using a spread spectrum technique and an integrated circuit device employing the spread spectrum clock generator.
2. Description of the Related Art
Signal processing devices integrated on a semiconductor chip, such integration being called a microprocessor, are often used for purposes such as generating a control signal for an appropriate control task from an input signal. In the microprocessor, circuitry to generate a clock for allowing the integrated signal processing devices and external memory devices to cooperate is used. Such clock generating circuitry is hereinafter referred to as a clock generator.
The clock generator to which a stable, periodic reference clock, which is typically generated by a crystal oscillator or an analog oscillator using resistor and capacitor time constant, is supplied from a pin provided on an integrated circuit structure, has a function to generate from the reference clock a high-frequency clock for allowing the signal processing devices in the integrated circuit structure and memory devices to cooperate.
However, the use of a highly stable reference clock generated by the crystal oscillator or the like may give rise to Electro Magnetic Interference to electronics outside the integrated circuit structure and it has been required to take a suitable shield technique that is capable of suppressing the Electro Magnetic Interference. As the shield technique, for example, an arrangement in which the circuit block containing the integrated circuit structure is surrounded with metal plates connected to GND (ground potential) at a low impedance was taken. To reduce electromagnetic emission that causes the Electro Magnetic Interference, methods for generating a reference clock with a frequency that varies in a predetermined cycle have been studied. Techniques for reducing the Electro Magnetic Interference are described in Patent Documents 1, 2, and 3.
An example of a prior art clock generator for reducing the ElectroMagnetic Interference is shown in FIG. 16. This clock generator comprises a phase locked loop (hereinafter reference to as a PLL) which is made up of a phase comparator (CMP) 1 to which a reference clock fr is input, a charge pump (CP) 2, a loop filter (LPF) 3, a voltage control oscillator (hereinafter referred to as a VCO) 4, and a divider (DIV) 5, the clock generator also comprising an address generator (AD_GEN) 40 to which the reference clock fr is also input and a lookup table (LTB) 41 (the clock generator configured in this way is discussed in Patent Document 1, for example). The method for generating a high-frequency clock by means of the PLL is well known and, moreover, the principle of generating a high-frequency clock with the PLL is described in Non-Patent Document 1; hence, its detailed description is omitted here. The PLL has a function to modulate the reference clock fr and output a high-frequency clock fo scaled up by a factor corresponding to a division number N of the divider 5.
The address generator 40 shown in FIG. 16 generates an address in the lookup table 41 in sync with the reference clock fr and the lookup table 41 outputs a division number of the divider 5 retrieved from that address. In the lookup table 41, a sine function or a predetermined function whose values are addressed is stored in advance. Address change depending on the reference clock fr changes the division number that is an integer output from the lookup table.
Division number change in turn changes the frequency of the high-frequency clock fo that is output from the PLL. Consequently, time during which the clock occupies the same frequency becomes shorter and the intensity of the Electro Magnetic Interference can be lessened. By setting an average value of the function that is stored in the lookup table 41 with regard to the time axis to N, the high-frequency clock fo obtained from the PLL has an average frequency fr×N, and, thus, a relatively stable high-frequency clock can be obtained.
Another example of a prior art clock generator to reduce the Electro Magnetic Interference, using the PLL, is shown in FIG. 17. This clock generator is made up of a phase comparator 1, to which the reference clock fr is input, a charge pump 2, a loop filter 3, a modulator (MOD) 29, a VCO 4, and a divider 5 (the clock generator configured in this way is discussed in Patent Document 2, for example) This clock generator generates a high-frequency clock by the PLL, in the respect of which, it is the same as the above-described prior art, but the modulator 29 is inserted between the loop filter 3 and the VCO 4. With the modulator 29 thus inserted to give a modulating signal mod which is any analog modulated signal, frequency modulation of the high-frequency clock fo can be performed. For example, by using a sine wave as the modulating signal mod, it can be expected to generate a highly precise spread spectrum clock.
An example of prior art for reducing the Electro Magnetic Interference by means of a divider is described in, for example, Patent Document 4. This method is to store random numbers in a lookup table and output a signal to control the division number from the lookup table in sync with the reference clock fr. Because the division number is controlled by a non-periodic control signal, divided clock frequencies can vary, free from periodicity.    [Patent Document 1]    Japanese Published Unexamined Patent Application No. H07-235862    [Patent Document 2]    Japanese Published Unexamined Patent Application No. 2002-246900    [Patent Document 3]    Japanese Published Unexamined Patent Application No. 2002-140130    [Patent Document 4]    Japanese Published Unexamined Patent Application No. 2000-228658    [Non-Patent Document 1]    “Design of Analog CMOS Integrated Circuits” by Prof. Behzad Razavi, pp. 532-562 and pp. 572-574, published on Aug. 12, 1999 from The McGraw-Hill Companies, Inc.